Full-swing source-follower leakage tolerant dynamic logic

ABSTRACT

An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.

FIELD

[0001] Embodiments of the present invention relate to digital circuits,and more specifically, to dynamic logic circuits.

BACKGROUND

[0002] Sub-threshold leakage currents in dynamic circuits may limitperformance as process technology leads to smaller and smaller devicesize. To maintain circuit robustness, designers have used variousapproaches, but with the result that circuit delay and performance maybe adversely affected. These issues are discussed in more detail byconsidering the prior art domino logic in FIG. 1.

[0003] The domino logic gate in FIG. 1 comprises dynamic stage 102 andstatic stage 104. In the particular example of FIG. 1, static stage 104is a single-input, single-output inverter, but other inverting staticlogic may be employed. nMOS (Metal Oxide Semiconductor) logic 108comprises one or more nMOSFETs (Metal Oxide Semiconductor Field EffectTransistor) to conditionally pull node 110 LOW during an evaluationphase, depending upon the input voltages at input ports 106. (Inputports 106 may actually consist of only one input port, e.g., if thedomino gate is an inverter gate.)

[0004] During an evaluation phase, clock signal φ is HIGH so thatpMOSFET 112 is OFF and nMOSFET 114 is ON to conditionally provide a lowimpedance path between node 110 and ground 128 at voltage V_(SS)depending upon the input voltages at input ports 106. During apre-charge phase, clock signal φ is LOW so that nMOSFET 114 is OFF andpMOSFET 112 is ON to pull node 110 HIGH by providing a low impedancepath between node 110 and power rail 126 at supply voltage V_(CC).

[0005] If the domino gate of FIG. 1 is not at a clock boundary, thennMOSFET 114 may be removed so that nMOS logic 108 is connected directlyto ground 128 if all input voltages are LOW during an evaluation phase.This is the reason for illustrating nMOSFET 114 with dashed lines. Ahalf-keeper comprising inverter 116 and pMOSFET 118 is designed tomaintain node 110 HIGH unless it is otherwise pulled LOW by nMOS logic108 during an evaluation phase. Only one domino gate is shown in FIG. 1,but in practice, a plurality of such gates are connected together toform a larger domino circuit. For example, output port 124 of the dominologic gate may be connected to an input port of another domino logicgate.

[0006] Sub-threshold leakage current in an nMOSFET comprisessource-drain current when the gate-to-source voltage V_(GS) is less thanthe threshold voltage V_(T). Consider the circuit of FIG. 1 during anevaluation phase in which the input voltages at input ports 106 are suchthat nMOS logic 108 does not pull node 110 LOW. (That is, the inputvoltages are such that the output logic voltage at output port 124 ofthe domino logic gate is supposed to be LOW.) Unless the circuit of FIG.1 is designed properly, sub-threshold leakage current through nMOS logic108 during the evaluation stage may prevent the half-keeper frommaintaining node 110 sufficiently HIGH, so that output port 124 mayprovide an incorrect logic level. One approach to mitigate this effectis to size the half-keeper larger so as to maintain acceptablerobustness. However, a larger half-keeper may cause evaluationcontention with nMOS logic 108 during an evaluation phase if nMOS logic108 tries to pull node 110 LOW, which may increase the delay of thedomino gate. Another approach is to employ high-V_(T)(high-threshold-voltage) nMOSFETs in MOS logic 108 to reduce the amountof sub-threshold leakage current. However, using high-V_(T) nMOSFETs inMOS logic 108 may increase the delay in the domino gate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a prior art domino logic gate.

[0008]FIG. 2 is an embodiment domino logic gate according to anembodiment of the present invention.

[0009]FIGS. 3A and 3B provide embodiments of a single-ended senseamplifier employed in the embodiment domino logic gate of FIG. 2.

DESCRIPTION OF EMBODIMENTS

[0010]FIG. 2 is a circuit for a domino logic gate according to anembodiment of the present invention. The domino gate of FIG. 2 is in itpre-charge phase when {overscore (φ)} is HIGH and is in its evaluationphase when {overscore (φ)} is LOW. The domino logic gate comprisesdynamic stage 202 and static stage 204. In the particular embodiment ofFIG. 2, static stage 204 is a single-input, single-output inverter, butother inverting static logic may be employed.

[0011] nMOS logic 208 comprises one or more nMOSFETs that conditionallyswitch ON to charge node 210 during an evaluation phase, depending uponthe input voltages at input ports 206. (Input ports 206 may actuallyconsist of one input port, e.g., if the domino logic gate is an invertergate.) During an evaluation phase, clock signal {overscore (φ)} is LOWso that nMOSFET 212 is OFF and pMOSFET 214 is ON so that a low impedancepath is conditionally provided between node 210 and power rail 226,depending upon the input voltages at input ports 206. Power rail 226 isat a supply voltage V_(CC). During a pre-charge phase, clock signal{overscore (φ)} is HIGH so that pMOSFET 214 is OFF and nMOSFET 212 is ONto discharge node 210 by providing a low impedance path between node 210and ground 228 at voltage V_(SS).

[0012] Note that we have referred to the condition in which the clocksignal {overscore (φ)} is HIGH as a pre-charge phase, even though node210 is actually being discharged by nMOSFET 212 during a pre-chargephase. Consequently, one may refer to this condition as a pre-dischargephase instead of a pre-charge phase. It is to be understood in theseletters patent that these terms may be used interchangeably, and thatfor simplicity the term pre-charge phase will be used here even thoughfor the embodiments of the present invention described herein a node isbeing discharged when the dynamic circuit enters its pre-charge phase.

[0013] If the domino gate of FIG. 2 is not at a clock boundary, then theinput voltages are LOW during a pre-charge phase, and consequentlypMOSFET 214 may be removed so that nMOS logic 208 is connected directlyto power rail 226. This is the reason for illustrating pMOSFET 214 withdashed lines.

[0014] Inverter 216 and nMOSFET 218 comprise a half-keeper. Thecombination of inverter 220 and pMOSFET 222 will be referred to as asingle-ended sense amplifier. Their roles will be discussed further whenconsidering the operation of the embodiment domino logic gate of FIG. 2,which is now described.

[0015] Consider the pre-charge (pre-discharge) phase in which the clocksignal {overscore (φ)} is HIGH, pMOSFET 214 is OFF (if present, such asfor a domino stage on a clock boundary), nMOSFET 212 is ON, and theinput voltages are LOW (if not on a clock boundary). nMOSFET 212 willturn ON and will discharge node 210. For example, for some embodiments,nMOSFET 212 may be sized large enough so that node 210 is brought LOW(V_(SS)). Node 210 is discharged to a low enough voltage so that thecombination of inverters 220 and 204 provide a LOW output voltage atoutput port 224. In this way, other domino gates connected to outputport 224 are not affected when in a pre-charge phase.

[0016] Now consider the evaluation phase in which the clock signal{overscore (φ)} is LOW, pMOSFET 214 is ON (if present), and nMOSFET 212is OFF. Suppose the input voltages at input ports 206 are such thatthere is no nMOSFET stack within nMOS logic 208 that is switched ON. Ifnode 210 was pulled LOW during the pre-charge phase, then sub-thresholdleakage current through nMOS logic 208 will charge node 210 to somevoltage dV above V_(SS) until the one or more nMOSFETs within nMOS logic208 with sources connected to node 210 are reverse-biased into theircutoff region and are strongly turned OFF. In this way, sub-thresholdleakage current is significantly reduced. Note that with node 210 atvoltage dV above V_(SS), the gate-to-source voltage V_(GS) for a nMOSFETwithin nMOS logic 208 having its source connected to node 210 isV_(GS)=−dV. Note also that as the node 210 charges, the reverse-biasincreases.

[0017] However, if the input voltages at input port 206 are such that anMOSFET stack within nMOS logic 208 is switched ON (a low impedance pathis provided between node 210 and power rail 214), then nMOS logic 208performs a fast pull-up operation on node 210 until it is pulled up toV_(CC)-V_(T). Then, the single-ended sense amplifier comprising inverter220 and pMOSFET 222 kicks in and continues to charge node 210 so that itis pulled HIGH (substantially to V_(CC)). In this way, a full-railtransition is provided. Because of this, and because node 210 isconnected to sources of nMOSFETs in nMOS logic 208, the domino logicgate of FIG. 2 may be referred to as a full-swing, source-followerdomino logic gate.

[0018] For some embodiments, nMOSFET 212 may not be sized sufficientlylarge enough completely discharge node 210 to LOW during a pre-chargephase, in which case the above description regarding the charging ofnode 210 by sub-threshold leakage current applies. In this case, node210 may already be at the voltage dV, or perhaps less than dV.Consequently, those nMOSFETs within nMOS logic 208 with sourcesconnected to node 210 may already be reverse-biased into their cutoffregion, or perhaps close to their cutoff region.

[0019] The half-keeper comprising nMOSFET 218 and inverter 216 is sizedto maintain node 210 at the small voltage dV above V_(SS) if node 210 isnot pulled to V_(CC)-V_(T) by nMOS logic 208.

[0020] An advantage of the embodiment of FIG. 2 over that of FIG. 1 isthat for process technologies in which sub-threshold leakage currentsneed to be considered, the half-keeper comprising nMOSFET 218 andinverter 216 may not need to be up-sized as aggressively becausesub-threshold currents in nMOS logic 208 are suppressed by the reversebias. As a result, performance may be maintained as process technologyscales to smaller device sizes.

[0021] Different embodiments for the single-ended sense amplifier may berealized. Two embodiments are provided in FIGS. 3A and 3B. FIG. 3A is astraightforward implementation of an inverter, comprising pMOSFET 302and nMOSFET 304, connected to pMOSFET 306. The embodiment of FIG. 3A maysuffer from leakage current when node 308 is at the voltage dV aboveV_(SS). Although nMOSFET 304 may not be turned ON strongly, the voltagedV+V_(SS) at node 308 may be such that leakage current flows throughnMOSFET 304, thereby wasting power. The embodiment of FIG. 3B may beconsidered a low-leakage single-ended sense amplifier. If node 310 is atthe voltage dV+V_(SS), then any leakage current through nMOSFET 312 willcause the voltage at node 314 to rise. The embodiment of FIG. 3B may bedesigned so that the voltage at node 314 rises to dV+V_(SS), in whichcase the gate-to-source voltage of nMOSFET 316 is zero and nMOSFET 316is turned OFF. In this way, leakage current is significantly reduced. Ineither embodiment, inverter 220 may be designed so as to be n-skewed.

What is claimed is:
 1. A dynamic circuit having an evaluation phase and a pre-charge phase, the dynamic circuit comprising: at least one input port having at least one input voltage; a node; at least one nMOSFET to conditionally switch ON to charge the node during an evaluation phase depending upon the at least one input voltage; and a transistor to discharge the node during a pre-charge phase.
 2. The dynamic circuit as set forth in claim 1, further comprising: a first inverter having an input port and an output port; and a pMOSFET having a gate connected to the output port of the first inverter, and having a drain connected to the input port of the first inverter; wherein the first inverter and pMOSFET are coupled to the node to charge the node when the at least one nMOSFET conditionally switches ON to charge the node.
 3. The dynamic circuit as set forth in claim 2, further comprising: a second inverter having an input port and an output port; a nMOSFET having a gate connected to the output port of the second inverter and a drain connected to the input port of the second inverter; and wherein the second inverter and nMOSFET are coupled to the node to maintain the node in a discharged state if not conditionally charged by the at least one nMOSFET switching ON.
 4. The dynamic circuit as set forth in claim 1, wherein the at least one nMOSFET conditionally switches ON to charge the node to a voltage V_(CC)-V_(T) depending upon the at least one input voltage, where V_(CC) is a supply voltage to the dynamic circuit and V_(T) is a threshold voltage of the at least one nMOSFET.
 5. The dynamic circuit as set forth in claim 4, further comprising: a first inverter having an input port and an output port; and a pMOSFET having a gate connected to the output port of the first inverter, and having a drain connected to the input port of the first inverter; wherein the first inverter and pMOSFET are coupled to the node to charge the node to the voltage V_(CC) when the at least one nMOSFET conditionally switches ON to charge the node to the voltage V_(CC)-V_(T).
 6. The dynamic circuit as set forth in claim 5, further comprising: a second inverter having an input port and an output port; a nMOSFET having a gate connected to the output port of the second inverter and a drain connected to the input port of the second inverter; and wherein the second inverter and nMOSFET are coupled to the node to maintain the node in a discharged state if not conditionally charged by the at least one nMOSFET switching ON.
 7. The dynamic circuit as set forth in claim 1, further comprising: a ground having a voltage V_(SS); wherein the at least one nMOSFET has sub-threshold leakage current to charge the node to a voltage dV above V_(SS) to reverse bias the at least one nMOSFET during at least a portion of an evaluation phase when the at least one nMOSFET is not switched ON.
 8. The dynamic circuit as set forth in claim 7, wherein the at least one nMOSFET conditionally switches ON to charge the node to a voltage V_(CC)-V_(T) during an evaluation phase depending upon the at least one input voltage, where V_(CC) is a supply voltage to the dynamic circuit and V_(T) is a threshold voltage of the at least one nMOSFET, wherein dV+V_(SS)<V_(CC)-V_(T).
 9. The dynamic circuit as set forth in claim 8, further comprising: a first inverter having an input port and an output port; and a pMOSFET having a gate connected to the output port of the first inverter, and having a drain connected to the input port of the first inverter; wherein the first inverter and pMOSFET are coupled to the node to charge the node to the voltage V_(CC) when the at least one nMOSFET conditionally switches ON to charge the node to the voltage V_(CC)-V_(T).
 10. The dynamic circuit as set forth in claim 9, further comprising: a second inverter having an input port and an output port; a nMOSFET having a gate connected to the output port of the second inverter and a drain connected to the input port of the second inverter; and wherein the second inverter and nMOSFET are coupled to the node to maintain the node at substantially the voltage dV above V_(SS) when the node is in a discharged state if not conditionally charged by the at least one nMOSFET switching ON.
 11. A dynamic circuit having an evaluation phase and a pre-charge phase, the dynamic circuit comprising: a power rail; a ground at voltage V_(SS); a node; at least one input port having at least one input voltage; at least one nMOSFET connected to the node so that during an evaluation phase a conditional low impedance path is provided between the node and the power rail depending upon the at least one input voltage; and a first nMOSFET having a drain connected to the node so that a low impedance path is provided between the node and the ground during a pre-charge phase.
 12. The dynamic circuit as set forth in claim 11, wherein during at least a portion of an evaluation phase when the at least one nMOSFET does not provide a low impedance path between the node and the power rail, the node is at a voltage dV above V_(SS) so that the at least one nMOSFET is reverse biased.
 13. The dynamic circuit as set forth in claim 12, further comprising: a first inverter having an input port connected to the node and an output port; and a second nMOSFET having a gate connected to the output port of the second inverter and a drain connected to the node.
 14. The dynamic circuit as set forth in claim 13, further comprising: a second inverter having an input port connected to the node and an output port; and a pMOSFET having a gate connected to the output port of the inverter and a drain connected to the node.
 15. The dynamic circuit as set forth in claim 1 1, further comprising: an inverter having an input port connected to the node and an output port; and a pMOSFET having a gate connected to the output port of the inverter and a drain connected to the node.
 16. The dynamic circuit as set forth in claim 12, further comprising: an inverter having an input port connected to the node and an output port; and a pMOSFET having a gate connected to the output port of the inverter and a drain connected to the node.
 17. A dynamic circuit having an evaluation phase and a pre-charge phase, the dynamic circuit comprising: a power rail having a supply voltage V_(CC); a ground having a voltage V_(SS); a node; at least one nMOSFET, having a threshold voltage V_(T), to charge the node to a voltage V_(CC)-V_(T) if ON during an evaluation phase.
 18. The dynamic circuit as set forth in claim 17, the at least one nMOSFET to charge the node to a voltage dV above V_(SS) if OFF during an evaluation phase, where dV+V_(SS)<V_(CC)−V_(T).
 19. The dynamic circuit as set forth in claim 18, wherein the at least one nMOSFET is reverse-biased if the node is at the voltage dV.
 20. The dynamic circuit as set forth in claim 18, further comprising: an inverter having an input port connected to the node and an output port; and a pMOSFET having a gate connected to the output port of the first inverter and a drain connected to the node to charge the node to the voltage V_(CC) if the at least one nMOSFET is ON during an evaluation phase. 